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FlashAttention-4 Guide: Blackwell Kernel Co-Design

FlashAttention-4 Architecture: Kernel Pipelining and Algorithm Co-Design for Asymmetric Hardware Scaling on NVIDIA Blackwell GPUs

Scaling transformer throughput across datacenter clusters forms the physical foundation of modern artificial intelligence: training frontier reasoning models, hosting high-concurrency enterprise inference engines, and executing high-throughput multimodal intelligence pipelines powered by AI Fetchly. Whether processing millions of web records gathered through intelligent web scraping or orchestrating high-velocity API data transformations with automated data fetching, the efficiency of core attention computation dictates server density, power budgets, and token generation costs.

Over the past four years, Tri Dao’s FlashAttention line has defined the GPU programming standard for exact attention:

  • FlashAttention-1 (2022): Introduced IO-awareness and online softmax tiling, fitting attention into SRAM and eliminating quadratic HBM read/write bottlenecks on Ampere (A100) GPUs.
  • FlashAttention-2 (2023): Parallelized sequence dimensions and reduced non-matmul FLOPs, achieving up to 73% theoretical peak utilization on Hopper (H100) GPUs.
  • FlashAttention-3 (2024): Exploited Hopper’s asynchronous Tensor Memory Accelerator (TMA) and warp-specialized WGMMA instructions to overlap compute and memory transfers.

However, the arrival of NVIDIA’s Blackwell architecture (SM100 / B200 / GB200) introduced a severe architectural challenge: asymmetric hardware scaling. On Blackwell, dense FP16/BF16 Tensor Core compute throughput doubled relative to Hopper, yet Shared Memory (SRAM) bandwidth, register file bandwidth, and non-matmul functional unit throughput scaled much more slowly. Standard attention algorithms—including FlashAttention-3—hit a wall on Blackwell: Tensor Cores spend half their time stalled waiting for softmax exponents or memory barrier synchronizations.

To solve this hardware mismatch, researchers Ted Zadouri, Markus Hoehnerbach, Jay Shah, Vijay Thakkar, and Tri Dao introduced FlashAttention-4: Algorithm and Kernel Pipelining Co-Design for Asymmetric Hardware Scaling (arXiv:2603.05451, presented at MLSys 2026).

FlashAttention-4 co-designs the mathematical tiling algorithm with Blackwell’s physical silicon. Written entirely in CuTe-DSL (NVIDIA’s next-generation Python-embedded domain-specific language), FlashAttention-4 targets Blackwell’s tcgen05 instructions, decouples GEMM computation from softmax evaluation via deep multi-stage software pipelining, and leverages cluster-wide TMA multicast. The resulting kernel achieves a historic 1613 TFLOPs/s (reaching 71% of Blackwell’s theoretical ceiling), delivering a 1.3x speedup over cuDNN 9.13 and 2.7x over OpenAI Triton.

In this comprehensive technical guide, we break down why Blackwell’s asymmetric scaling breaks legacy attention kernels, examine FlashAttention-4’s algorithmic co-design and CuTe-DSL implementation, contrast FA4 against competing GPU kernels, construct an educational Python/PyTorch simulation of its pipelining mechanics, and analyze production deployment strategies.

The Problem: Asymmetric Hardware Scaling on NVIDIA Blackwell

To understand why FlashAttention-4 was necessary, we must examine the architectural divergence between GPU generations: the Tensor Core versus memory bandwidth imbalance, the softmax execution bottleneck, and the limits of CUDA C++ and Triton compilers.

The Hardware Imbalance on NVIDIA Blackwell (SM100): Hopper (H100) ──▶ Blackwell (B200) Generational Transition │ ├── 1. Tensor Core Scaling: │ └── FP16/BF16 Dense Tensor Core FLOPS doubled (~2.25x increase to 2250+ TFLOPs!). │ ├── 2. The Asymmetry Bottleneck: │ └── Shared Memory (SRAM) capacity & bandwidth grew by only ~1.3x. │ └── Non-Matmul ALUs (FP32 Add, Exp, Max) grew by only ~1.2x. │ └── ❌ Fatal Flaw: Tensor Cores calculate Q*K^T twice as fast, but the hardware │ cannot move tiles or compute softmax exponentials fast enough to feed them! │ ├── 3. The Compiler Abstraction Wall: │ └── Triton & standard CUTLASS C++ struggle to manage Blackwell's complex │ tensor memory accelerator (TMA) multi-stage asynchronous barriers. │ └── 4. FlashAttention-4 Resolution: ├── Algorithmic Co-Design: Reorders online softmax into multi-stage pipelined tiles. ├── CuTe-DSL Metaprogramming: Python-embedded tile layouts lowering directly to tcgen05! └── Multicast TMA: Shares K/V blocks across SM clusters to bypass memory buses!

The Ratio Divergence in Modern Silicon

For a kernel to achieve peak hardware utilization, the ratio of floating-point compute to memory access must match the GPU’s physical balance.

Between NVIDIA Hopper (SM90) and Blackwell (SM100):

  • Tensor Core Compute: Doubled to over $2,250 \text{ TFLOPs/s}$ in dense FP16.
  • SRAM Bandwidth: Increased by only $\approx 35%$.
  • High-Bandwidth Memory (HBM3e) Bandwidth: Increased from $3.35 \text{ TB/s}$ to $8.0 \text{ TB/s}$ ($\approx 2.4\times$).

Because the arithmetic compute grew far faster than internal register and shared memory buses, the arithmetic intensity required to saturate Blackwell’s Tensor Cores skyrocketed. Algorithms that were balanced on Hopper suddenly became severely memory- and latency-bound on Blackwell.

The Non-Matmul Softmax Bottleneck

In standard FlashAttention, each tile iteration computes two General Matrix Multiplications (GEMMs) and an elementwise softmax reduction:

  1. $\mathbf{S}{\text{tile}} = \mathbf{Q}{\text{tile}} \mathbf{K}_{\text{tile}}^T$ (Dense GEMM on Tensor Cores)
  2. $\mathbf{P}{\text{tile}} = \text{Softmax}(\mathbf{S}{\text{tile}})$ (Non-GEMM operations: Max, Subtract, Exp, Sum on CUDA Cores)
  3. $\mathbf{O}{\text{tile}} = \mathbf{P}{\text{tile}} \mathbf{V}_{\text{tile}}$ (Dense GEMM on Tensor Cores)

On Hopper, step 2 was fast enough that Tensor Cores experienced minimal stalls between step 1 and step 3.

On Blackwell, however, step 1 and step 3 execute twice as fast. As a consequence, step 2 (the row-wise maximum and exponential calculation) becomes a crippling bottleneck. If Tensor Cores must pause for 30 cycles while standard FP32 ALUs normalize the attention matrix, hardware utilization plunges from 70% down to 40%.

FlashAttention-4 Architecture: CuTe-DSL and Multi-Stage Kernel Pipelining

FlashAttention-4 overcomes asymmetric hardware scaling through an integrated algorithm-kernel co-design strategy: deep software pipelining, tcgen05 instruction targeting, and Python-native CuTe-DSL programming.

┌────────────────────────────────────────────────────────────────────────────────────────┐ │ FLASHATTENTION-4 PIPELINED EXECUTION │ ├────────────────────────────────────────────────────────────────────────────────────────┤ │ │ │ STAGE 1: ASYNCHRONOUS TENSOR MEMORY ACCELERATOR (TMA) INGESTION │ │ ├── Multicast TMA loads Key/Value tiles from HBM directly into SMEM across SM cluster│ │ └── Bypasses register files and avoids CPU/thread block involvement │ │ │ │ STAGE 2: DECOUPLED MATRIX MULTIPLY (tcgen05 WGMMA) │ │ ├── Warps execute Q * K^T on Blackwell Tensor Cores asynchronously │ │ └── Output written directly to accumulator registers │ │ │ │ STAGE 3: MULTI-STAGE SOFTWARE PIPELINED SOFTMAX │ │ ├── Pipelined Exponentiation: Overlaps Exp(S) computation with next TMA load │ │ └── Micro-tiling: Normalizes sub-tiles incrementally to avoid thread stalls │ │ │ │ STAGE 4: ACCUMULATED OUTPUT GEMM & TMA WRITE │ │ ├── P * V computed on Tensor Cores with zero register spilling │ │ └── Emits exact, mathematically identical attention output: O in R^{B x S x D} │ │ │ └────────────────────────────────────────────────────────────────────────────────────────┘

1. targeting Blackwell’s tcgen05 Architecture

Blackwell introduces the tcgen05 instruction set—a generational evolution over Hopper’s WGMMA (Warp Group Matrix Multiply Accumulate). tcgen05 allows warp groups to launch matrix multiplications that read directly from shared memory and write directly into specialized accumulator registers with minimal instruction dispatch overhead.

FlashAttention-4 restructures tile dimensions to match Blackwell’s native tcgen05 tensor shapes:

  • Uses larger tile sizes (e.g., $192 \times 128$ or $128 \times 128$) to maximize Tensor Core occupancy.
  • Employs TMA Multicast: when multiple thread blocks across an SM cluster require identical Key and Value matrices, Blackwell’s memory crossbar broadcasts the tile simultaneously to multiple shared memory blocks, slashing HBM traffic by up to $2\times$.

2. Deep Software Pipelining

To prevent the non-matmul softmax operations from stalling the Tensor Cores, FlashAttention-4 organizes execution into an asynchronous 4-stage software pipeline:

  • Stage $i$ (TMA): Loading the next $K_{i+1}$ and $V_{i+1}$ tiles from HBM into Shared Memory.
  • Stage $i-1$ (GEMM 1): Computing $\mathbf{S}_i = \mathbf{Q} \mathbf{K}_i^T$ using tcgen05.
  • Stage $i-2$ (Softmax): Computing the row-wise max, exponentials, and running normalizers on the previously calculated $\mathbf{S}_{i-1}$.
  • Stage $i-3$ (GEMM 2): Computing $\mathbf{O} += \mathbf{P}{i-2} \mathbf{V}{i-2}$.

By overlapping the execution of these four stages across specialized warp groups, the Tensor Cores never sit idle: while CUDA cores calculate exponentials for block $i-2$, the Tensor Cores are already computing matrix multiplications for block $i-1$.

3. Pure CuTe-DSL Implementation

A remarkable engineering feature of FlashAttention-4 is that it is written entirely in CuTe-DSL embedded in Python, without a single line of raw CUDA C++:

  • CuTe-DSL provides Python-level abstractions for layout algebra, multi-dimensional tensor indexing, and asynchronous hardware barriers.
  • The CuTe-DSL compiler lowering directly generates PTX assembly optimized for Blackwell SM100.
  • This eliminates the fragile C++ template bloat that characterized earlier CUTLASS libraries, making the kernel easier to modify, audit, and optimize for custom head dimensions.

Architectural Comparison: FlashAttention-4 vs. Competing Attention Kernels

To evaluate FlashAttention-4’s engineering performance, we compare it against Standard PyTorch SDPA, FlashAttention-2, FlashAttention-3, OpenAI Triton, and cuDNN 9.13 on NVIDIA Blackwell SM100.

Metric / DimensionStandard PyTorch SDPAFlashAttention-2FlashAttention-3OpenAI Triton KernelNVIDIA cuDNN 9.13FlashAttention-4 (MLSys 2026)
Target GPU ArchitectureUniversalAmpere (A100) / HopperHopper (H100)General PurposeBlackwell (B200)Blackwell (SM100 Native)
Peak Throughput (TFLOPs)~520 TFLOPs~720 TFLOPs~980 TFLOPs~590 TFLOPs~1240 TFLOPs1613 TFLOPs / Sec (71% Peak)
Language / ImplementationC++ / ATenCUDA C++ (CUTLASS)CUDA C++ (CUTLASS)Triton DSL (Python)Vendor Proprietary C++CuTe-DSL (Python Embedded)
Instruction TargetStandard GEMMmma.syncHopper WGMMAGeneric PTXtcgen05tcgen05 + TMA Multicast
Softmax OverlappingNone (Sequential)PartialWarp SpecializedLimitedProprietary4-Stage Deep Pipelined
Speedup over Triton0.9x1.2x1.6x1.0x (Baseline)2.1x2.7x Speedup over Triton
Speedup over cuDNN0.4x0.6x0.8x0.5x1.0x (Baseline)1.3x Speedup over cuDNN
Exact Output Guarantee100% Exact100% Exact100% Exact100% Exact100% Exact100% Exact (Mathematically Lossless)

Why FlashAttention-4 Outperforms Triton by 2.7x

OpenAI Triton provides a clean programming model, but its compiler abstraction hides hardware-level asynchronous barriers and cluster memory multicast. On Blackwell, managing the fine-grained synchronization between TMA memory arrival and tcgen05 instruction dispatch requires tile-level control that Triton cannot yet express. CuTe-DSL gives FlashAttention-4 direct control over hardware barriers, preventing pipeline stalls.

Outperforming Vendor-Tuned cuDNN 9.13

NVIDIA’s proprietary cuDNN library is heavily optimized for general enterprise workloads. However, FlashAttention-4’s 4-stage software pipelining and custom micro-tiling achieve 1.3x higher throughput than cuDNN 9.13, proving that academic algorithm-kernel co-design can beat closed-source vendor implementations.

End-to-End PyTorch Simulation: Pipelined Online Softmax Attention

While the production FlashAttention-4 kernel compiles via CuTe-DSL to Blackwell PTX assembly, understanding its algorithmic breakthrough requires inspecting the mathematical tiled online softmax loop. Below is a self-contained PyTorch implementation demonstrating the tiled online softmax, running normalization tracking, and memory-bounded accumulation.

""" FlashAttention Online Softmax & Tiling Simulation Educational implementation of the IO-aware tiled attention mechanics underlying FlashAttention-4. Reference: "FlashAttention-4: Algorithm and Kernel Pipelining Co-Design" (MLSys 2026) Authors: Ted Zadouri, Markus Hoehnerbach, Jay Shah, Vijay Thakkar, Tri Dao """ import math import torch import torch.nn as nn from typing import Tuple def flash_attention_online_cpu_sim( Q: torch.Tensor, K: torch.Tensor, V: torch.Tensor, block_size_q: int = 64, block_size_kv: int = 64 ) -> torch.Tensor: """ Simulates the tiled online softmax algorithm of FlashAttention. Args: Q: [Batch, NumHeads, SeqLenQ, HeadDim] K: [Batch, NumHeads, SeqLenKV, HeadDim] V: [Batch, NumHeads, SeqLenKV, HeadDim] Returns: O: Exact attention output [Batch, NumHeads, SeqLenQ, HeadDim] """ batch_size, num_heads, seq_len_q, head_dim = Q.shape _, _, seq_len_kv, _ = K.shape scale = 1.0 / math.sqrt(head_dim) # Initialize output accumulator and online normalization statistics O = torch.zeros_like(Q) # Running row-wise maximum: m_i m = torch.full((batch_size, num_heads, seq_len_q, 1), -float("inf"), device=Q.device) # Running row-wise denominator sum: l_i l = torch.zeros((batch_size, num_heads, seq_len_q, 1), device=Q.device) num_blocks_q = (seq_len_q + block_size_q - 1) // block_size_q num_blocks_kv = (seq_len_kv + block_size_kv - 1) // block_size_kv # Outer loop: Iterate over query blocks (stored in fast SRAM) for i in range(num_blocks_q): q_start = i * block_size_q q_end = min(q_start + block_size_q, seq_len_q) q_tile = Q[:, :, q_start:q_end, :] # [B, H, B_q, D] m_i = m[:, :, q_start:q_end, :] # [B, H, B_q, 1] l_i = l[:, :, q_start:q_end, :] # [B, H, B_q, 1] o_i = O[:, :, q_start:q_end, :] # [B, H, B_q, D] # Inner loop: Stream key/value blocks (pipelined via TMA in hardware) for j in range(num_blocks_kv): kv_start = j * block_size_kv kv_end = min(kv_start + block_size_kv, seq_len_kv) k_tile = K[:, :, kv_start:kv_end, :] # [B, H, B_kv, D] v_tile = V[:, :, kv_start:kv_end, :] # [B, H, B_kv, D] # 1. GEMM 1: S_tile = Q_tile * K_tile^T s_tile = torch.matmul(q_tile, k_tile.transpose(-1, -2)) * scale # [B, H, B_q, B_kv] # 2. Online Softmax update # Compute local tile maximum m_tilde, _ = torch.max(s_tile, dim=-1, keepdim=True) # [B, H, B_q, 1] m_new = torch.maximum(m_i, m_tilde) # Compute exponentiated scores p_tilde = torch.exp(s_tile - m_new) # [B, H, B_q, B_kv] l_tilde = torch.sum(p_tilde, dim=-1, keepdim=True) # [B, H, B_q, 1] # Compute scale factor for previous accumulator alpha = torch.exp(m_i - m_new) l_new = alpha * l_i + l_tilde # 3. GEMM 2 & Output Rescaling: # Rescale existing output tile and add new contribution o_i = (alpha * l_i * o_i + torch.matmul(p_tilde, v_tile)) / l_new # Update running stats m_i = m_new l_i = l_new # Write finished block back to global memory O[:, :, q_start:q_end, :] = o_i m[:, :, q_start:q_end, :] = m_i l[:, :, q_start:q_end, :] = l_i return O # --- Verification Execution --- if __name__ == "__main__": device = "cuda" if torch.cuda.is_available() else "cpu" print(f"Testing FlashAttention Online Softmax Algorithm on {device}...") torch.manual_seed(42) B, H, S, D = 2, 4, 256, 64 q = torch.randn(B, H, S, D, device=device) k = torch.randn(B, H, S, D, device=device) v = torch.randn(B, H, S, D, device=device) # 1. Compute exact reference attention via standard PyTorch scores_ref = torch.matmul(q, k.transpose(-1, -2)) / (D ** 0.5) attn_ref = torch.softmax(scores_ref, dim=-1) out_ref = torch.matmul(attn_ref, v) # 2. Compute via Tiled Online Softmax Simulation out_tiled = flash_attention_online_cpu_sim(q, k, v, block_size_q=64, block_size_kv=64) # 3. Check mathematical equivalence max_diff = torch.max(torch.abs(out_ref - out_tiled)).item() print(f"Max Absolute Error vs Reference: {max_diff:.8e}") assert max_diff < 1e-5, "Tiled online attention deviates from reference!" print("Exact mathematical fidelity confirmed!")

Enterprise Strategy: Deploying FlashAttention-4 with aiFetchly

In modern enterprise architectures, language models operate as the core compute engine of autonomous document intelligence, web crawling, and real-time knowledge synthesis. These systems ingest heterogeneous feeds through enterprise web scraping and unified API integrations.

┌────────────────────────────────────────────────────────────────────────────────────────┐ │ ENTERPRISE HIGH-THROUGHPUT PIPELINE: AIFETCHLY + FLASHATTENTION-4 │ ├────────────────────────────────────────────────────────────────────────────────────────┤ │ │ │ 1. Automated Document Ingestion (<InternalLink feature="data-fetching" text="aiFetchly Data Fetching" />) │ │ └── Ingest millions of regulatory disclosures, SEC filings & technical manuals │ │ │ │ 2. Blackwell Accelerated Serving Cluster (GB200 / B200 Nodes) │ │ ├── FlashAttention-4 Kernel Runtime: Slashes attention latency to sub-millisecond │ │ └── Sustains 1613 TFLOPs/s across 128k+ sequence context windows │ │ │ │ 3. Ultra-Dense Server Concurrency │ │ └── 2.7x higher serving goodput over standard Triton-based inference runtimes │ │ └── 100% mathematically exact outputs (zero approximation degradation) │ │ │ │ 4. Commercial Economics & Production Scaling (<InternalLink feature="pricing" text="aiFetchly Pricing" />) │ │ └── Slashes per-token datacenter hosting expenditure by over 40% │ │ │ └────────────────────────────────────────────────────────────────────────────────────────┘

When building automated workflows that serve high query volumes over extended context windows, memory-bound attention often drives up infrastructure costs. By pairing AI Fetchly‘s structured data feeds with FlashAttention-4:

  1. Maximum Hardware Efficiency: Extract 71% of Blackwell’s theoretical silicon ceiling, eliminating idle GPU bubbles during long-context prefill.
  2. Lossless Quality Assurance: Maintain mathematically exact FP16/BF16 attention weights without sacrificing precision.
  3. Scalable Enterprise Economics: To design a custom multimodal ingestion and generation architecture tailored to your organization’s volume, review our enterprise pricing models and developer guides in our developer documentation.

Summary & Key Takeaways

FlashAttention-4 sets a new standard for GPU algorithm-hardware co-design:

  • Asymmetric Scaling Solution: Overcomes Blackwell’s hardware imbalance where Tensor Core compute doubled while memory bandwidth and non-matmul ALUs lagged behind.
  • CuTe-DSL Metaprogramming: Replaces complex CUDA C++ template programming with clean, Python-embedded CuTe-DSL that compiles directly to optimized PTX assembly.
  • 4-Stage Software Pipelining: Concurrently overlaps asynchronous TMA multicast, tcgen05 Tensor Core GEMMs, and online softmax exponent calculations.
  • Historic Hardware Utilization: Reaches 1613 TFLOPs/s (71% utilization) on Blackwell SM100, delivering a 1.3x speedup over cuDNN 9.13 and 2.7x over OpenAI Triton.

By aligning mathematical tiling directly with the physical architecture of modern silicon, FlashAttention-4 provides the computational engine required to power the next generation of frontier AI models.