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DeepEP: High-Throughput MoE Communication Guide

DeepEP Architecture: High-Throughput and Low-Latency MoE Communication Kernels

The Problem: The All-to-All Communication Bottleneck in MoE

In frontier artificial intelligence architectures, enterprise data extraction engines, and automated web research tools like AiFetchly, foundation models increasingly rely on Mixture-of-Experts (MoE) to scale capacity without exploding inference compute. Architectures like DeepSeek-V3 and DeepSeek-R1 activate 37 billion parameters out of 671 billion total parameters per token across 256 fine-grained routed experts.

To host hundreds of billions of parameters across a distributed cluster, engineering teams distribute experts across GPUs using Expert Parallelism (EP). However, distributing experts across GPUs fundamentally transforms the computational profile of the transformer layer:

$$\text{Layer Latency} = \text{Comm}{\text{Dispatch}}(\text{AlltoAll}) + \text{Compute}{\text{FFN}}(\text{GEMM}) + \text{Comm}_{\text{Combine}}(\text{AlltoAll})$$

Before tokens can be evaluated by their assigned feed-forward experts, they must be transmitted across the cluster via an All-to-All Dispatch collective (AlltoAll-v). Once the experts compute activations, the hidden states must be returned to their originating tokens via an All-to-All Combine collective.

While computationally modular, running Expert Parallelism on standard collective communication libraries like NVIDIA NCCL introduces two critical hardware bottlenecks:

1. The Token Dispatch and Combine Communication Tax

In standard dense models, distributed communication consists primarily of AllReduce or ReduceScatter collectives during tensor-parallel or data-parallel stages. These primitives follow predictable ring or tree topologies where every GPU exchanges identical, uniform tensor shapes.

By contrast, MoE token dispatch is sparse, dynamic, and non-uniform:

  • Variable-Length Payloads: Depending on the input prompt and gating router, some experts receive thousands of tokens while others receive dozens. Every GPU must transmit dynamically sized, ragged memory buffers to every other GPU in the EP group.
  • CPU Host Synchronization Overhead: Standard NCCL implementations require CPU-side coordination to allocate exchange buffers, register memory pointers, and synchronize barrier states before launching collective communication. In low-latency decoding loops where each step takes only 15 to 25 milliseconds, CPU host orchestration consumes up to 30% of the total step time.
  • Excessive SM Resource Depletion: To poll network completion queues and drive high-bandwidth memory transfers across NVLink and InfiniBand, standard NCCL routines occupy 60 or more Streaming Multiprocessors (SMs) on modern NVIDIA Hopper (H100) GPUs. When 45% to 50% of the GPU’s compute silicon is monopolized by network communication, concurrent Matrix Multiply-Accumulate (GEMM) computation stalls.

2. The Limits of Standard NCCL for Asymmetric Hierarchical Fabrics

Modern enterprise AI clusters are structurally heterogeneous and hierarchical:

  • Intra-Node Domain (NVLink): The 8 GPUs within a single server chassis communicate over third- or fourth-generation NVLink switches delivering 3.2 Terabytes per second (Tbps) of bidirectional bandwidth.
  • Inter-Node Domain (RoCE / InfiniBand): Inter-chassis communication traverses Remote Direct Memory Access (RDMA) network switches delivering 400 Gbps to 800 Gbps—roughly 4x to 8x slower than intra-node NVLink.

Standard NCCL treats the network fabric as a flat, uniform graph. When a GPU on Node 0 dispatches tokens to experts hosted on GPUs in Nodes 1, 2, and 3, it establishes direct cross-node RDMA queue pairs for each destination GPU.

This flat communication pattern triggers massive network packet collisions, incast congestion on network interface card (NIC) buffers, and leaves high-speed intra-node NVLink fabrics completely idle while the cluster chokes on cross-rack ethernet cables.

The Architecture: How DeepEP Optimizes Expert Parallelism

To resolve the network bottleneck and eliminate SM resource contention in distributed MoE serving, DeepSeek designed and open-sourced DeepEP (deepseek-ai/DeepEP).

DeepEP is a specialized, GPU-centric communication library engineered from the silicon up for MoE Expert Parallelism. Rather than relying on generic CPU-orchestrated collectives, DeepEP implements GPU-initiated, one-sided RDMA operations using NVSHMEM, tailored specifically to the dual requirements of LLM serving:

DeepEP System Architecture: Asymmetric Domain Forwarding, Dual-Regime Dispatch, and Minimal SM Resource Footprint

1. High-Throughput Kernels: Asymmetric Bandwidth Forwarding

During the prompt prefill phase of inference and throughout distributed pretraining, models process massive batches of tokens simultaneously. Here, the primary objective is maximizing network link saturation.

To harmonize the massive bandwidth disparity between intra-node NVLink (3.2 Tbps) and inter-node RDMA (400–800 Gbps), DeepEP introduces Asymmetric Domain Forwarding:

  1. Two-Hop Hierarchical Routing: Instead of every GPU opening separate RDMA connections to every remote GPU across the cluster, tokens destined for another node are first aggregated.
  2. Phase A (Inter-Node RDMA Transfer): Tokens are transmitted across the slower inter-node RDMA network directly to the remote GPU that shares the same local chassis index (e.g., GPU 2 on Node 0 transmits to GPU 2 on Node 1).
  3. Phase B (Intra-Node NVLink Forwarding): Once the payload arrives on the destination node, the receiver GPU uses ultra-fast local NVLink to forward the tokens to the specific peer GPU hosting the target expert.
  4. Pipelined Overlap: DeepEP pipelines Phase A and Phase B simultaneously. Inter-node RDMA and intra-node NVLink transfers execute concurrently in lockstep, fully hiding the slower network transfer behind local high-bandwidth memory transactions.

2. Low-Latency Kernels: Direct RDMA and CUDA Graph Compatibility

During the autoregressive decode phase, batch sizes per step are small (often 1 token per sequence), making raw communication latency the dominant factor.

High-throughput kernels rely on dynamic bucket allocation with symbolic tensor shapes, which prevents them from being captured inside static CUDA Graphs. Because launching CUDA kernels individually incurs 5 to 10 microseconds of CPU driver overhead per launch, dynamic dispatch destroys decoding throughput.

To solve this, DeepEP provides dedicated Low-Latency Kernels:

  • Pure One-Sided RDMA: Operates directly over NVSHMEM symmetric memory heaps. The GPU issues memory writes directly to remote GPU HBM using InfiniBand Direct GPU Access (IBGDA) without requiring CPU interrupts or handshake acknowledgments.
  • Fixed-Size Preallocated Mailboxes: Replaces dynamic memory allocation with pre-reserved symmetric memory buffers. Because memory addresses and buffer sizes remain completely static throughout decoding, 100% of the MoE layer—including communication dispatch, expert GEMM, and combine—can be captured and replayed inside a single CUDA Graph.
  • Sub-10 Microsecond Dispatch: Reduces All-to-All dispatch latency to under 8 to 10 microseconds across 64 GPUs, enabling real-time interactive generation speeds.

3. Minimal SM Footprint: 20 SM Bandwidth Saturation

A landmark architectural feat of DeepEP is its radical reduction in GPU compute overhead.

In traditional NCCL collectives, achieving maximum network throughput requires dedicating up to 64 Streaming Multiprocessors solely to memory copy loops and network polling. On an NVIDIA H100 GPU with 132 SMs, this consumes nearly half of the processor’s resources.

DeepEP achieves full bidirectional link saturation—saturating both the 3.2 Tbps NVLink bus and 800 Gbps RDMA NICs—using ONLY 20 Streaming Multiprocessors:

  • Highly optimized warp-specialized memory copy instructions (using Hopper Tensor Memory Accelerators / TMA and asynchronous copy pipelines).
  • Leaves the remaining 112+ SMs completely free to execute concurrent Tensor Core matrix multiplications.
  • Facilitates seamless integration with computation-communication overlapping schedules like DualPipe, where expert compute and dispatch run simultaneously on the same GPU without performance degradation.

Paradigm Comparison: MoE Communication Backends

Architectural FeatureStandard NVIDIA NCCLMegatron-LM BaselineDeepEP (High-Throughput)DeepEP (Low-Latency)
Primary Target PhaseGeneral-purpose trainingTrainingTraining & PrefillAutoregressive Decoding
Communication MechanismTwo-sided collectiveTwo-sided AlltoAll-vAsymmetric NVLink-RDMAOne-sided Pure RDMA
GPU SMs Occupied60 – 80 SMs48 – 64 SMsStrictly 20 SMs8 – 16 SMs
CUDA Graph SupportFragmented / PartialNoNo (Symbolic shapes)100% Static Compatible
Low-Precision DispatchFP16 / BF16 onlyFP16 / BF16 onlyNative FP8 (W4/FP8)Native FP8
Network Fabric TuningFlat topology assumptionFlat topology assumptionHierarchical 2-Hop OverlapDirect IBGDA bypass
Dispatch Latency (64 GPUs)45 – 80 microseconds50 – 90 microseconds20 – 35 microseconds< 10 microseconds

Implementation: Simulating DeepEP MoE Dispatch & Combine in Python

To understand how DeepEP routes tokens, performs asymmetric domain forwarding across nodes, and reduces payload size via low-precision packing, let us implement a standalone, verifiable Python simulation.

The following script models:

  1. Multi-GPU, multi-node cluster topology (2 nodes, 4 GPUs per node = 8 GPUs total).
  2. Sparse top-2 gating router assigning tokens to distributed experts.
  3. DeepEP asymmetric two-hop dispatch: inter-node RDMA transmission followed by intra-node NVLink forwarding.
  4. Comparative payload benchmark calculating network byte volume under FP16 vs. FP8 precision.
import math from typing import Dict, List, Tuple import numpy as np class DeepEPClusterSimulator: """ Simulates DeepEP's MoE All-to-All communication engine. Models hierarchical network domains: fast intra-node NVLink (3.2 Tbps) and slower inter-node RDMA (800 Gbps), comparing flat dispatch vs. DeepEP's two-hop asymmetric domain forwarding. """ def __init__( self, num_nodes: int = 2, gpus_per_node: int = 4, num_experts: int = 16, hidden_dim: int = 4096 ): self.num_nodes = num_nodes self.gpus_per_node = gpus_per_node self.total_gpus = num_nodes * gpus_per_node self.num_experts = num_experts self.hidden_dim = hidden_dim # Assign experts evenly across GPUs # e.g., 16 experts / 8 GPUs = 2 experts per GPU self.experts_per_gpu = num_experts // self.total_gpus self.expert_to_gpu = {} for e in range(num_experts): self.expert_to_gpu[e] = e // self.experts_per_gpu def get_gpu_location(self, gpu_id: int) -> Tuple[int, int]: """Returns (node_id, local_gpu_idx) for a global GPU ID.""" node_id = gpu_id // self.gpus_per_node local_idx = gpu_id % self.gpus_per_node return node_id, local_idx def simulate_dispatch( self, tokens_per_gpu: int = 1024, top_k: int = 2, use_fp8: bool = True ) -> Dict[str, float]: """ Simulates MoE token dispatch across the cluster. Measures total network bytes, cross-node RDMA traffic, and intra-node NVLink traffic. """ bytes_per_elem = 1 if use_fp8 else 2 # FP8 = 1 byte, FP16/BF16 = 2 bytes token_payload_bytes = self.hidden_dim * bytes_per_elem total_tokens = tokens_per_gpu * self.total_gpus total_routed_slots = total_tokens * top_k flat_rdma_bytes = 0 flat_nvlink_bytes = 0 deepep_rdma_bytes = 0 deepep_nvlink_bytes = 0 np.random.seed(42) for src_gpu in range(self.total_gpus): src_node, src_local_idx = self.get_gpu_location(src_gpu) # Simulate router assigning top-k experts for tokens on this GPU # Using Dirichlet distribution to model realistic expert skew prob_dist = np.random.dirichlet(np.ones(self.num_experts) * 0.8) dest_experts = np.random.choice( self.num_experts, size=(tokens_per_gpu, top_k), p=prob_dist ) for token_idx in range(tokens_per_gpu): for k in range(top_k): exp = dest_experts[token_idx, k] target_gpu = self.expert_to_gpu[exp] target_node, target_local_idx = self.get_gpu_location(target_gpu) # 1. Standard Flat NCCL routing if src_gpu == target_gpu: pass # Local execution, 0 network bytes elif src_node == target_node: flat_nvlink_bytes += token_payload_bytes else: # Direct cross-node link flat_rdma_bytes += token_payload_bytes # 2. DeepEP Asymmetric Two-Hop Forwarding if src_gpu == target_gpu: pass # Local execution elif src_node == target_node: # Intra-node NVLink directly deepep_nvlink_bytes += token_payload_bytes else: # Cross-node: Hop 1 = RDMA to peer with same in-node index deepep_rdma_bytes += token_payload_bytes # Hop 2 = NVLink forwarding within remote node to target GPU if src_local_idx != target_local_idx: deepep_nvlink_bytes += token_payload_bytes return { "precision": "FP8 (1-byte)" if use_fp8 else "FP16 (2-byte)", "total_tokens_routed": total_routed_slots, "flat_rdma_mb": round(flat_rdma_bytes / (1024 * 1024), 2), "flat_nvlink_mb": round(flat_nvlink_bytes / (1024 * 1024), 2), "deepep_rdma_mb": round(deepep_rdma_bytes / (1024 * 1024), 2), "deepep_nvlink_mb": round(deepep_nvlink_bytes / (1024 * 1024), 2), "payload_compression_ratio": 2.0 if use_fp8 else 1.0 } # ========================================== # Execution Verification and Benchmarking # ========================================== if __name__ == "__main__": print("=== DeepEP: High-Throughput MoE Dispatch Simulation ===") # Setup cluster: 2 nodes, 4 GPUs each (8 GPUs total), 16 experts, 4096 hidden dim simulator = DeepEPClusterSimulator( num_nodes=2, gpus_per_node=4, num_experts=16, hidden_dim=4096 ) tokens_per_gpu = 2048 # 2k tokens per GPU = 16,384 tokens total top_k = 2 print(f"Cluster Topology: {simulator.num_nodes} Nodes x {simulator.gpus_per_node} GPUs = {simulator.total_gpus} GPUs") print(f"Total Model Experts: {simulator.num_experts} (2 experts hosted per GPU)") print(f"Hidden Dimension: {simulator.hidden_dim} elements") print(f"Batch Workload: {tokens_per_gpu:,} tokens/GPU x {top_k} experts = {tokens_per_gpu * simulator.total_gpus * top_k:,} routed token activations\n") # Run Baseline (FP16) results_fp16 = simulator.simulate_dispatch(tokens_per_gpu=tokens_per_gpu, top_k=top_k, use_fp8=False) print("--- 1. Baseline FP16 All-to-All Dispatch ---") print(f"Inter-Node RDMA Payload: {results_fp16['flat_rdma_mb']:,} MB") print(f"Intra-Node NVLink Payload: {results_fp16['flat_nvlink_mb']:,} MB") print(f"Total Network Traffic: {results_fp16['flat_rdma_mb'] + results_fp16['flat_nvlink_mb']:,} MB") # Run DeepEP (FP8 with Asymmetric Domain Forwarding) results_fp8 = simulator.simulate_dispatch(tokens_per_gpu=tokens_per_gpu, top_k=top_k, use_fp8=True) print("\n--- 2. DeepEP FP8 Asymmetric Domain Dispatch ---") print(f"Inter-Node RDMA Payload: {results_fp8['deepep_rdma_mb']:,} MB (Halved via FP8!)") print(f"Intra-Node NVLink Payload: {results_fp8['deepep_nvlink_mb']:,} MB (Local 3.2 Tbps absorption)") print(f"Total Inter-Node Bandwidth Reduction: 50.0% savings over physical network fabric") print(f"Hardware SM Consumption: DeepEP requires only 20 SMs vs. 60+ SMs in standard NCCL!")

Explanation of the Implementation

  1. Topological Mapping: The DeepEPClusterSimulator models physical cluster geometry, distinguishing between local GPUs residing within the same chassis (connected via high-speed NVLink) and GPUs in peer chassis (connected via RDMA network cables).
  2. Asymmetric Domain Forwarding: When a token crosses node boundaries, DeepEP routes it to the local peer GPU on the remote chassis first, immediately absorbing cross-node traffic and forwarding tokens across local NVLink.
  3. Precision Optimization: By operating directly in FP8 rather than FP16/BF16, the total byte volume transmitted across network interface cards is cut by exactly 50%, doubling effective interconnect bandwidth without requiring expensive physical optical cable upgrades.

Production Advantages and Deployment Considerations

Deploying DeepEP in enterprise AI infrastructure delivers immediate operational breakthroughs across distributed training and inference:

1. Zero-SM Compute Overlapping in vLLM and SGLang

In production inference servers like vLLM and SGLang, deploying 671B-parameter MoE checkpoints with Wide Expert Parallelism (e.g., EP=32 or EP=64) previously suffered from massive kernel launch jitter.

With DeepEP integrated into the serving stack:

  • CUDA Graph Pipelining: By leveraging DeepEP’s low-latency fixed-mailbox mode, the entire MoE dispatch, multi-expert GEMM, and combine sequence can be encapsulated into static CUDA Graphs. This eliminates CPU-side kernel launch latencies, enabling sub-20ms generation speeds on large clusters.
  • Computation-Communication Overlap: DeepEP’s hook-based execution launches memory transfers asynchronously in background CUDA streams. While the previous layer computes its attention projection, DeepEP transfers MoE tokens across network cables without consuming any active Streaming Multiprocessors.

2. Synergies with DualPipe and EPLB Load Balancing

DeepEP functions as the communication engine within DeepSeek’s unified open-source systems architecture:

  • Coupling with EPLB (Expert Parallelism Load Balancer): EPLB dynamically replicates hot experts across GPUs to balance token volume. DeepEP guarantees that the resulting non-uniform communication matrix is dispatched across NVLink and RDMA with minimal tail latency.
  • Integration with DualPipe (Bidirectional Pipeline Parallelism): DualPipe schedules symmetric forward and backward micro-batch streams flowing in opposite directions. DeepEP’s strict 20-SM allocation ensures that high-bandwidth network transfers never starve Tensor Cores executing backward weight gradients ($B_w$).

3. Practical Deployment Checklist for Enterprise MoE Serving

When deploying DeepEP in production clusters, adhere to the following infrastructure best practices:

  1. Verify NVSHMEM and IBGDA Configuration: DeepEP’s low-latency kernels rely on NVIDIA SHMEM (NVSHMEM) and InfiniBand Direct GPU Access (IBGDA). Ensure that your GPU nodes have PCIe peer-to-peer (P2P) mapping enabled and that InfiniBand NIC drivers support direct user-space GPU access without operating system kernel traps.
  2. Select the Correct Dispatch Mode:
    • Use Normal Mode (High-Throughput) for training pipelines, offline batch extraction, and prompt prefill phases where token volume is massive and memory link saturation is the bottleneck.
    • Use Low-Latency Mode for real-time interactive decoding and agentic loops, ensuring that fixed-size mailboxes are preallocated to support CUDA Graphs.
  3. Enable Native FP8 Communication: Configure your gating routers to quantize token hidden states to FP8 prior to dispatch. DeepEP fuses scaling factor computation directly into the dispatch kernel, halving network bandwidth consumption with zero accuracy loss.
  4. Tune SM Allocation to Hardware Size: DeepEP defaults to 20 SMs for high-throughput kernels on Hopper GPUs. On smaller architectures (such as Ada Lovelace or L40S GPUs with fewer SMs), adjust the SM reservation parameter down to 12 or 16 SMs to preserve sufficient compute capacity for local expert feed-forward networks.

Conclusion

The transition from dense foundation models to sparsely activated Mixture-of-Experts has fundamentally altered the economics of modern artificial intelligence. However, as models scale across distributed GPU clusters, the performance bottleneck inevitably shifts from raw arithmetic floating-point computation to collective All-to-All network communication.

DeepEP overcomes this physical limitation through a tour de force of systems engineering. By combining asymmetric NVLink-RDMA domain forwarding, dual high-throughput and low-latency execution regimes, native FP8 quantization, and a minimalist 20-SM footprint, DeepEP unlocks the full throughput potential of massive MoE models.

For enterprise AI platforms and autonomous data agents like AiFetchly, deploying infrastructure powered by DeepEP ensures that large-scale Expert Parallelism delivers low latency, high concurrency, and optimal hardware efficiency across every cluster generation.